1. Field
This document relates to a gate shift register and a display device comprising the same.
2. Related Art
Various flat panel displays capable of reducing the weight and the size of a cathode ray tube have been developed and have been put on the market. In general, a scan driving circuit of the flat panel display sequentially supplies a scan pulse to scan lines using a gate shift register.
The gate shift register of the scan driving circuit comprises a plurality of stages each including a plurality of thin film transistors (TFTs). The stages are cascade-connected to one another and sequentially generate scan pulses. FIG. 1 shows an example of an nth stage for generating an nth scan pulse Vg(n). FIG. 2 is a waveform diagram for explaining the operation of FIG. 1. Transistors to be described hereinafter may be implemented as TFTs.
Referring to FIGS. 1 and 2, the nth stage comprises a Q node for controlling a switching operation of a pull-up transistor Tpu and a QB node for controlling a switching operation of a pull-down transistor Tpd. The pull-up transistor Tpu is turned on in a first output period X1 in which the potential VQ of the Q node is maintained at a bootstrapping level BH to output a shift clock signal CLKn as an nth scan pulse Vg(n) of a gate high voltage VGH. The pull-up transistor Tpu is turned off during a second output period X2 in which the potential V1 of the Q node is maintained at a discharge level L. The potential VQB of the QB node is maintained at the discharge level L during the first output period X1 and at a charge level H during the second output period X2. Due to the potential VQB of the QB node, the pull-down transistor Tpd is turned on during the second output period X2 to output a low-potential voltage VSS as an nth scan pulse Vg(n) of a gate low voltage VGL. In a third output period X3 prior to the first output period X1, the potential VQ of the Q node is maintained at the charge level H, and the potential VQB of the QB node is maintained at the discharge level L.
First, fifth, and sixth transistors T1, T5, and T6 connected to the Q node control the potential VQ of the Q node by a switching operation. The first transistor T1 charges the Q node in response to a set signal SET during a third output period X3. The set signal SET may be selected as an (n−1)th scan pulse Vg(n−1). The fifth transistor T5 discharges the Q node in response to a reset signal RESET during the second output period X2. The reset signal RESET may be selected as an (n+1)th scan pulse Vg(n+1). The sixth transistor T6 maintains the Q node at the discharge level L when the QB node is maintained at the charge level H during the second output period X2.
Second to fourth transistors T2, T3, and T4 connected to the QB node control the potential VQB of the QB node by a switching operation. The second transistor T2 discharges the QB node in response to a reset signal RESET during the third output period X3. The third transistor T3 discharges the QB node in accordance with the potential VQ of the Q node in the third output period X3 and the first output period X1. The fourth transistor T4 supplies a high-potential voltage VDD to the QB node. The high-potential voltage VDD is charged in the QB node in the second output period X2 in which the second and third transistors T2 and T3 are turned off.
In this manner, the Q node and QB node in each stage are charged and discharged, respectively, or vice versa. That is, when the Q node is charged (including bootstrapping), the QB node is discharged; or conversely, when the Q node is discharged, the QB node is charged. A scan pulse has to be generated at the gate high voltage VGH only for a short period of time X1 to charge a data voltage in 1 horizontal pixel line and at the gate low voltage VGL for the remaining period. Accordingly, a period (i.e., second output period X2) of one frame, in which the potential VQB of the QB node is maintained at the charge level H, is much longer than a period (i.e., first and third output periods X1 and X3) in which the potential VQB of the QB node is maintained at the discharge level L.
In general, when a gate voltage of the same polarity is applied to gate electrodes of the TFTs for a long time, gate-bias stress is increased so that the threshold voltage of the TFTs is increased. A drain-source current Ids of the TFTs is determined by the gate-source voltage Vgs of the TFTs and the threshold voltage of the TFTs. As shown in FIG. 4, if the threshold voltage of the TFTs increases with the passage of driving time, the drain-source current Ids of the TFTs is reduced.
In FIGS. 1 to 3, a gate electrode of the pull-down transistor Tpd and a gate electrode of the sixth transistor T6 are connected to the QB node which is maintained at the charge level H for most of the time X2 of one frame. Accordingly, the pull-down transistor Tpd and the sixth transistor T6 may be degraded due to a threshold voltage shift with the passage of driving time. Particularly, if the high-potential voltage VDD is applied to the QB node at a constant charge level H from an initial period of driving, such degradation is accelerated. If the pull-down transistor Tpd is degraded, a scan pulse is not maintained at the gate low voltage VGL but may gradually rise or be generated in undesired multiple waveforms.